During the production of integrated semiconductor memories, for example DRAM (dynamic random access memory)—semiconductor memories, operating parameters are defined for operation of the semiconductor memory, and are programmed in the semiconductor memory. The operating parameters include, for example, internal voltage levels which are produced by voltage generators for the semiconductor memory and are fed to an internal voltage network in order to supply further components. Further operating parameters which can be defined include refresh frequencies by which the memory cells are refreshed during normal operation of the semiconductor memory. The operating parameters are in general preset in the semiconductor memory by the programming of fuse elements.
In addition to fuse elements, specific registers for programming of operating parameters are also available on the semiconductor chip. Particularly in the case of integrated semiconductor memories, a so-called mode register is preferably used for this purpose. A mode register set command is applied to the address connections of the semiconductor memory in order to program the mode register. Customary operating parameters, such as a burst length or a CAS latency, are then written to the mode register via the address pins.
The reading of operating parameters that have already been programmed in again can be carried out at any time just by using specific test modes. In this case, test modes are produced at a low frequency on a small number of module pins since a high degree of test parallelism when using slower testers is generally a primary factor in production.
German Patent Document No. DE 101 24 735 C1 describes a method for testing semiconductor chips, in which a check mode is carried out after setting and before carrying out the actual test mode, in which the status of the test mode used in the chip is read in a defined format. Test mode settings can be checked by the application of characteristic bit sequences, and registers which are used for storage of a test result by test modes, can be read. The method according to the invention thus offers the capability to check the state of all of the test modes and registers for a semiconductor chip to be tested, before the actual test is carried out in the chip, so that confidence is obtained that the test has been initiated correctly before the test results are obtained.
Since, in general, test modes are used only within production, the input/output protocol is, however, highly simplified. When a test mode for reading an operating parameter or a test result is activated after the application of a specific bit sequence to the address connections, then the corresponding data can normally be read only by a specific tester, which has previously been appropriately programmed. This is because, in general, the writing and reading of operating parameters is not matched to a standard interface or a standard protocol which is used for writing and reading data during normal operation of the integrated semiconductor memory device.
Operating parameters are therefore not input and output by application of control commands which are used for writing and reading data in accordance with the standard input/output protocol during normal operation of the integrated semiconductor memory device, but by the application of a test mode signal to the address connections. At the moment, it is possible for test purposes to read a large number of the operating parameters via the data connections, but this is not done at the standard operating speed at which the data is also read from the memory cell array. Instead, test data or operating parameters in the case of memory chips which already use a double data rate protocol is or are often still output using the single data rate protocol. Furthermore, the reading of test results or operating parameters is in general also independent of any data validity signal, the so-called data queue strobe signal (DQS signal).
Furthermore, certain registers, such as the mode register, are used only as pure input registers at the moment. External access to the mode register can be gained only via the address connections, although these are not bidirectional connections and therefore cannot also be used for outputting data. The operating parameters stored therein can thus also not be read via a test mode. At the end of the manufacturing process, it must therefore be assumed that the mode register has been correctly programmed.
Since an application generally accesses a memory chip only via the standard input/output interface and via the standard input/output protocol, operating parameters cannot be read at all, or can be read only in a restricted form, at the moment on customer-specific platforms such as the motherboard of a computer. A further disadvantage of the use of test modes for writing and reading operating parameters occurs when using modules. A memory module such as this has memory components which can be addressed in parallel and are shielded from a controller module by the actual computer platform. In the case of a so-called fully buffered DIMM module, the address, command and data pins of the individual memory components on the module can, for example, no longer be addressed directly externally. Instead of this, the individual memory components in the module are accessed via the common controller module. These are in general addressed by a high-frequency bus protocol in order to interchange data with the individual memory components using a standard DRAM protocol. However, since the address connections can be used only to access all the components at the same time, the mode registers of the individual memory components, for example, can be programmed only jointly. The same operating parameters are thus stored in all of the mode registers of the individual memory components. It is thus impossible to set the operating parameters on a component-specific basis.